1. Field of the Invention
The present invention relates to component-embedded substrates incorporating components such as capacitors, chip resistors, chip coils, ICs, and so on, in a resin.
2. Description of the Related Art
Recently, various types of component-embedded substrates have been proposed in which electronic components such as capacitors, chip resistors, chip coils, ICs, and so on, are embedded in a highly-integrated and highly-functional manner as electronic apparatuses become smaller in size and higher in performance.
In such a component-embedded substrate, components are mounted, for example, on a multilayer-structured substrate (multilayer printed-wiring board or the like), a transfer plate on which wiring has been carried out, or the like. The substrate, the transfer plate, or the like with the components mounted thereon is integrated by being embedded in the resin. In order to ensure electrical conductivity between the upper side and the lower side of the substrate and/or between the layers in the substrate, via holes are formed by laser irradiation so that in-plane conductors disposed on the upper surface and the lower surface of a component-embedded layer of the substrate are electrically conducted. Further via-hole conductors are formed by plating the interior of each of the via holes or filling conductive paste therein. Through these via-hole conductors, a surface layer and a rear layer of the substrate, and the surface layer and the embedded components, are made to be electrically conducted therebetween so as to be electrically connected.
FIG. 9 is a cross-sectional view of a component-embedded substrate formed in a related art, in which a component-embedded substrate 500 embedding a ceramic capacitor 501 therein, which is an electronic component, is illustrated as an example. The configuration of the substrate is as follows.
The ceramic capacitor 501 is adhered on a printed-wiring board 502 with a non-conductive adhesive 503, the printed-wiring board 502 includes an insulating base material 504 and wiring patterns 505A, 505B formed on the upper surface and the lower surface of the insulating base material 504, respectively, and the wiring patterns 505A, 505B are electrically connected with each other via through-holes 506. Each of the through-holes 506 is configured by forming a penetrating hole in the insulating base material 504 and thereafter carrying out plating of a conductive material, such as copper plating on the inner wall of the penetrating hole or filling a conductive material such as solder or conductive paste in the penetrating hole. An insulating resin layer 507 serving as an insulating layer is laminated and molded on the upper surface of the printed-wiring board 502 so as to cover the ceramic capacitor 501.
Wiring layers 508 are formed on the insulating resin layer 507. The wiring layers 508 are electrically connected with wiring patterns 505A on the upper surface side of the printed-wiring board 502 and terminal electrodes 501A of the ceramic capacitor 501 through via-hole conductors 510 and 511 respectively. Each of the via-hole conductors 510, 511 is formed by, for example, carrying out plating on a via hole having been formed by laser processing in the insulating resin layer 507 (for example, see Japanese Patent No. 4089273, especially paragraphs 0041 through 0048, and FIG. 2)).
Meanwhile, in the case of a component-embedded substrate formed in an existing method, such as the component-embedded substrate 500 shown in FIG. 9, via holes are formed first in the insulating resin layer 507 by laser irradiation, and then the via-hole conductors 510 and 511 are formed. However, because of difference in depth of these via holes, laser processing conditions need to be changed for each individual via hole having a different depth. This makes the manufacturing process extremely complex and may lead to a risk of increase in costs due to the increased complexity of the manufacturing process.
In addition, a via hole that penetrates through the insulating resin layer 507 in an up-down direction is required to have a larger diameter and a longer length as the depth of the insulating resin layer 507 increases in dimension. Accordingly, there has been a risk of generating a problem in that the area to be used for mounting and wiring on the upper surface side of the insulating resin layer 57 may be limited.
Furthermore, in the case where wiring is needed to be routed between the layers, a wiring layer for routing the wiring is needed to be formed additionally through another manufacturing method such as a buildup method. Therefore, there has been a risk of generating a problem in that the number of processes to be carried out may be increased.